An operation of the respective means of the mentioned apparatus is controlled by at least one timing signal produced by timing control circuit in order to execute a desired program. Such an apparatus has been heretofore generally used as a principal section, i.e., a program processing section of every information handling instrument from a large-scale computer to a micro-computer.
This apparatus normally comprises a memory for storing a group of instructions (commands, subroutines, microprograms, etc.) which are required for executing a program. Data is stored in a binary coded form. A circuit is provided for designating a particular instruction in the memory (an addressing circuit), and another circuit for reading the designated instruction from the memory. A circuit temporarily holds the read instruction (an instruction register), while another circuit decodes the read instruction (a decoder). At least one control signal is generated on the basis of the decoded result (a timing control circuit) and a circuit responds to the control signal for executing the processing determined by the instruction (an execution circuit). The addressing circuit includes an address register, whose content represents an address for the memory.
Accordingly, by sequentially modifying the content of the address register, instructions required for executing a given program are successively read out of the memory into the instruction register. The instructions designate an operation of the execution circuit.There are many varieties of instructions such as, for example, calculation instructions, data transfer instructions, a subroutine call instruction, a jump instruction, etc.
It is to be noted that an instruction has to be executed within a predetermined period. This execution period is defined by at least one cycle time of a machine (normally called "machine cycle"). Furthermore, the execution period of an instruction is not always constant for every instruction. In other words, a number of necessary machine cycles may be determined depending upon the instruction. For instance, for an instruction to merely add the content of an a single register to the content of a another single register, only one machine cycle suffices. However, an addition instruction to add the content of a memory location whose address is designated by a content of an a pair of registers to the content of an a single register, necessitates two machine cycles. Moreover, some of complexed instructions may require 5 machine cycles, for example or 6 machine cycles. Accordingly, a sum of the machine cycles allotted to the respective instructions, is a processing time of the program.
On the other hand, a number of bits of an instruction that can be read out of a memory during one access is equal to a number of bits that can be carried by a data bus. That is, if a data bus consists of a one-bit line, then an instruction code of one bit can be read. If a data bus consists of a 4-bit line, then an instruction code of 4 bits can be read out in parallel in the same timing. Normally, one instruction is coded with a plurality of bits. In order to achieve a speed-up of processing, a design is made such that an instruction code of a plurality of bits may be read out in parallel. For instance, 4 bits, 8 bits, 16 bits, etc. are simultaneously read out of a memory as a unit (one byte.
Further, if each one instruction is limited to one byte, then a number of available instructions would be limited. For example, if one byte consists of 4 bits, then the number of the available instructions is 2.sup.4 =16. In order to increase the number of the available instructions, it is only necessary to increase the number of bits per one byte. However, in that case, a number of wirings for a data bus or an address bus is increased, and so this is not favorable, especially in a small-sized type of machines.
Therefore, in the prior art, it was contemplated that, to overcome this shortcoming, it was necessary to increase a number of bytes per instruction. In this case, as a matter of course, a number of accesses to a memory is increased. For instance, if one instruction consists of 3 bytes, then three successive accesses to the memory are required. To that end, an addressing circuit must perform a processing by modifying a content of an address register three times. Normally, the respective bytes forming one instruction are alotted in consecutive address spaces. Accordingly, the addressing circuit has a facility for sequentially adding "one" to an address of a leading byte of an instruction (increment facility). However, at least one machine cycle is generaly necessitated for one memory access; for instance in order to read a 3-byte instruction at least 3 machine cycles are required. Furthermore, additional machine cycles are also required for processing the read instruction. Therefore, if a number of bytes in an instruction is increased, then a processing speed is correspondingly lowered, and this was an inevitable shortcoming in the prior art.
On the other hand, in order to achieve a speed-up of data processing, it may be conceived to increase a frequency of a clock signal for controlling the minimum operation timing of an apparatus. However, integrated circuit elements which can follow such a high-speed clock signal have not been mass-produced so far. Even if integrated circuit elements, which are operable in response to the high-frequency clock signal should be mass produced, it would be naturally expected that a still further high-speed program processing is desired.
On the other hand, as would be understood from checking the execution steps of many programs, all of those instructions, which are read out of a memory by address designation, are not always to be executed. It is difficult for a programmer to control a sequence of memory accesses corresponding to every programming condition. Therefore, the program sometimes contains instructions which are not to be executed, although they are read out of the memory by the memory access.
Further, there is frequently an occasion when a programmer makes a program to prohibit the execution of an accessed instruction under a predetermined condition. On this occasion, the execution of the instruction is prohibited by another instruction or by a control signal from a condition detect circuit which is working independently of instructions. Of course, there are some cases where a condition of the apparatus is judged by an instruction and the execution of the instruction which is read out of the memory is prohibited, according to the judged condition.
In the prior art, the instruction for cancelling or inhibiting the execution has to be exchanged to a non-operation (NOP) instruction. This NOP instruction is an instruction that keeps a condition in an apparatus as it is. However, an execution period of the NOP instruction has to be equal to an essential execution period alotted to the instruction for the inhibited execution. For instance, if an instruction, which should be inhibited, is a 2-machine cycle instruction, the NOP instruction necessitates two machine cycles. If a canceled instruction is a 5-machine cycle-instruction, the NOP instruction needs five machine cycles in its processing.
Although this NOP instruction is necessary in a program execution, a time period for its execution should be as short as possible. However, in the prior art, the time period of the NOP instruction can not be shortened because of the necessity for making the memory access.